Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same, including a gate electrode material in a recess or a buried gate cell structure, a polysilicon material doped with impurities over a sidewall of a recess located over the gate electrode material, and a junction formed using an annealing or a rapid thermal annealing (RTA) process, thereby establishing an overlap thickness between a gate electrode material of a buried gate and a junction.
In the case where a general transistor is formed on a semiconductor substrate, a method of forming a gate over the semiconductor substrate and doping impurities into both sides of the gate so as to form a source and a drain has been used. As the data storage capacity of a semiconductor memory device increases, a unit cell size is gradually decreased. That is, a design rule for a capacitor and a transistor in the unit cell has been reduced. Thus, while a channel length of a cell transistor is gradually decreased, a short channel effect, a Drain Induced Barrier Lower (DIBL) phenomenon, etc. occur in a conventional transistor, and thus operational reliability is decreased. In order to maintain a threshold voltage at a desirable level under an influence from a short channel effect and a DIBL phenomenon, a concentration of impurities in a channel may be increased.
However, if a high concentration of impurities is applied to a channel region of a device which is subject to a design rule of 100 nm or less, an electric field of a Storage Node (SN) junction is increased, thereby lowering refresh characteristics of a semiconductor memory device. In order to solve this problem, a cell transistor having a three-dimensional channel structure in which a channel extends in a vertical direction is used such that a desirable channel length of a cell transistor is maintained even when a design rule is decreased. That is, even when a channel width in a horizontal direction is short, since a channel length in a vertical direction is secured, an impurity doping concentration may be reduced and thus refresh characteristics are prevented from being lowered.
In addition, as the degree of integration in a semiconductor device is increased, a distance between a word line coupled to a cell transistor and a bit line coupled to the cell transistor is gradually reduced. As a result, a parasitic capacitance is increased and an operation margin of a sense amplifier (sense-amp) that amplifies data transmitted via the bit line is deteriorated, reducing reliability of the semiconductor device. In order to solve the above-mentioned shortcomings while simultaneously reducing a parasitic capacitance between a bit line and a word line, a buried word line structure in which a word line is formed only in a recess instead of over an upper part of a semiconductor substrate has been proposed. The buried word line structure forms a conductive material in a recess formed in a semiconductor substrate, and covers an upper part of the conductive material with an insulation film such that the word line is buried in the semiconductor substrate. As a result, the buried word line structure can be electrically isolated from a bit line formed over a semiconductor substrate.
However, a buried word line (buried gate) structure has some disadvantages. First, a leakage current caused by a Gate Induced Drain Leakage (GIDL) of a semiconductor device is increased between a conductive material (gate electrode) and an N-type junction or between a conductive material (gate electrode) and a storage node contact. Second, refresh characteristics of the semiconductor device are deteriorated due to GIDL. In order to substantially prevent a leakage current caused by GIDL from being increased, large amounts of conductive material (gate electrode) of the buried word line (buried gate) need to be etched so that an overlap region between the storage node contact and the conductive material (gate electrode) can be minimized. However, if large amounts of the conductive material (gate electrode) of such a buried word line (buried gate) are etched, a resistance of the buried word line (buried gate) increases even though a leakage current caused by GIDL characteristics can be prevented. Thus, an operation speed of the semiconductor device slows down.
As described above, it is difficult to consistently form a region overlapping the buried word line (buried gate) and a junction. The junction couples the buried word line and a source/drain region. That is, if an overlap region between the buried gate and the junction in the buried gate formation process is small in size, channel resistance is unavoidably increased, resulting in a tWR (Write Recovery time) margin failure. If the overlap region between the buried gate and the junction is large in size, a Gate Induced Drain Leakage (GIDL) is increased, resulting in a pause failure.